Zvue Media Player Memory & Registers

 
Memory Map

It looks like there isn't that much flexibilty for addressing with this processor - each chip select is tied to a particular fixed address range, so there isn't that much room to deviate. The configuration registers do allow for a lot of variation in timing.

SDRAM
FLASH
Configuration Registers

FLASH Memory:
EIM (External Interface Module) Configuration
Address
 Register
 Value
 Enabled?
0x00220000
 CS0U Chip Select 0 Upper Control 0x00000A00
0x00220004 CS0L Chip Select 0 Lower Control
 0x00000D01
 CSEN=1 (enabled)
0x00220008 CS1U Chip Select 1 Upper Control
 0x00000000
0x0022000C CS1L Chip Select 1 Lower Control
 0x00000802
 CSEN=0 (not enabled)
0x00220010 CS2U Chip Select 2 Upper Control
 0x00000000
0x00220014 CS2L Chip Select 2 Lower Control
 0x00000802 CSEN=0 (not enabled)
0x00220018 CS3U Chip Select 3 Upper Control
 0x00000000
0x0022001C CS3L Chip Select 3 Lower Control
 0x00000802 CSEN=0 (not enabled)
0x00220020 CS4U Chip Select 4 Upper Control
 0x00000000
0x00220024 CS4L Chip Select 4 Lower Control
 0x00000802 CSEN=0 (not enabled)
0x00220028 CS5U Chip Select 5 Upper Control
 0x00000000
0x0022002C CS5L Chip Select 5 Lower Control
 0x00000802 CSEN=0 (not enabled)
0x00220030 EIM Configuration Register 0x00000000

To come: SDRAM configuration registers.


Video Memory
It's in the SDRAM at a funny location. I'll get more specific.

General Purpose Input/Output (GPIO) Configuration

This processor has some of the most sophisticiated GPIO I have ever seen - each pin is configuratble in 131,072 ways!  I guess the silicon for this functionality is nearly free, so we'll see more of this in the future.

Port A
 Port B Port C
 Port D
Offset
 Reg
 Name
 Value
 Value
 Value
 Value
x+
Base address
 0x021c000
 0x021c100
 0x021c200
 0x021c300
00
 DDIR Data Direction Register 0x00000040 0x00000000 0x00000020 0x00000000
04
 OCR1 Output Configuration Register 1 0x00003000 0x00000000 0x00000C00 0x00000000
08
 OCR2 Output Configuration Register 2
 0x00000000 0x00000000 0x00000000 0x00000000
0C
 ICONFA1 Input Configuration Register A1 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
10
 ICONFA2 Input Configuration Register A2 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
14
 ICONFB1 Input Configuration Register B1 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
18
 ICONFB2
 Input Configuration Register B2
 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
1C
 DR
 Data Register 0x00000000 0x00000000 0x00000020 0x00000000
20
 GIUS
 GPIO In Use Register 0x00C27FFF 0xFFFFC0FF 0x0007FE3F 0x8000023F
24
 SSR
 Sample Status Register 0x00DAFFBE 0xFFBFEF00 0x0000FFF8 0xE04E71C0
28
 ICR1
 Interrupt Configuration Register 1 0x00000000 0x00000000 0x00000000 0x00000000
2C
 ICR2
 Interrupt Configuration Register 2
 0x00000000 0x00000000 0x00000000 0x00000000
30
 IMR
 Interrupt Mask Register 0x00000000 0x00000000 0x00000000 0x00000000
34
 ISR Interrupt Status Register 0x00000000 0x00000000 0x00000000 0x00000000
38
 GPR
 General Purpose Register 0x00000000 0x00000000 0x00000000 0x00000000
3C
 SWR
 Software Reset Register 0x00000000 0x00000000 0x00000000 0x00000000
40
 PUEN
 Pull_Up Enable Register 0xFFFFFFFC 0xFFFF3FFF 0xF910F7FF 0x7FFFFDFF

The GIUS register says which pins are used for peripherial (bit=0) and which pins are used for GPIO (bit=1). Here are some interesting subsystems:
Subsystem
 Pin Range
 Usage
I2C
 PA15-16
 some
SPI2
 PD7-10
 some
SPI1
 PC13-17
 some - confirmed connected to ACC connector.
UART1
 PC11-12
 GPIO
SSI0
 PC3-8
 some
UART2
 PB28-31
 GPIO
SSI1
 PB14-19
 GPIO




ACC Connector
5 pins, pinout to be determined.



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